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Why Serial faster than parallel?

Why Serial faster than parallel?


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Mbps, Gbps: one million bits per second, one billion bits per second

skew: Time deviation, A than B fast / slow second, one second is called skew

PCB: printed circuit board, which is the most circuit board

IO: input-output circuit

SerDes: serial to parallel, parallel to serial

Others say the fastest mouth consistent, we have to calculate. The industry is large-scale application of 28Gbps SerDes, pass a bit as long as 35.7 picoseconds, this time to light in a vacuum can go one centimeter, even the cornea to the retina are not enough. Which fast?

Let me talk about my answer, why faster than the serial interface parallel interface? Because the serial features and application scenarios, determine which is more suitable for some awareness of single channel rate design methods that are used in parallel is not appropriate.

Discuss this issue, we must first clear definition of what is a parallel interface (parallel link)? What serial interface (serial link)? This can be noisy day.

Parallel representative of DDR, said: “I am a pure lineage outstanding representative of the parallel port, each 8bit be provided with a pair DQS as the clock line, each bit must be synchronized to this DQS up, skew exceeded will not work, 64 DDR3-1600 total bandwidth to 100Gbps, which serial do “? I sneer, said: “Do not think I do not know your number, you do not look IO is a 1.6G, memory controller you are generally four parallel 400M, you have to quietly do something parallel to serial, then output. Moreover, you need to transfer 64bit data 80 full rate DQ / DQS line, but also the root of half-rate command 20 address lines, on average, less than 1G a line. ”

XAUI raised their hands and asked: “What am I XAUI serial port must be set 16 differential lines 8, 4 4 reading groups write, lack of any one group does not meet the agreement, looking very parallel ah??” 32-bit PCI-E also waiting for answers to look concerned.

We first define so: in a separate channel, simultaneous transmission 1bit each serial port, each bit of the plurality of parallel transmission simultaneously.

Standard serial port such as XAUI, HDMI, etc., each pair of differential lines form a channel (channel), whether successful transmission of each channel can not depend on other channels. And this DDR, 10 lines form a channel, while each pass 8bit, a bit wrong, only to re-pass, it is the standard parallel port, and chip-to-serial and IO are not related, does not affect the characterization. According to this definition, we look at how the various interface protocols divide it? I think it has been very clear, single channel transmission rate measure, serial faster in general. The next question is, why?

This is an electrical problem, but first and foremost an economic problem.

Any kind of agreement, but to improve the overall bandwidth are two ways, first of all to improve the transfer rate of a single line, followed by only increasing the number of wires. Increasing the number of lines is too expensive, and now the first chip IO often very nervous, but also increases the IO PAD catch additional ESD and area; increase the package and PCB additional lines more complex and more expensive which needless to say, for some basic agreement with the cable that is unacceptable. Are you willing to plug 16 or a network cable? Access TV time like a line of HDMI, or five lines of RGB + audio? @Arthur Wang also mentioned 150 meters long. . . . . . Moreover, even these parallel lines matches the length, head to think big.

Historically, engineers have really done first serial port, speed is not enough no option but to add the wire parallel tears, until they found the three magic weapons to speed, parallel power is not as strong, just as @auxten said. But inside the chip, the cost of increased bus width is not high, so the CPU which has a 1024-bit data bus is not surprising.

To improve the transmission rate of a single line, we have to be talked about analog circuit engineer three magic weapons, the differential signal (differential signaling), clock – Data Recovery (Clock-Data Recovery, referred to as CDR), and the channel homogenization (Channel Equalization , Eq).

The benefits of differential signals, nothing more than anti-interference ability, the introduction of noise is relatively small, although the two lines have to be, but the speed is increased from a few to hundreds of M G, is still very worthwhile.

CDR benefits @ Gong Liming also said, the elimination of skew, reduce power consumption and clock noise (but more out of the CDR circuit itself power consumption and noise), while avoiding electromagnetic interference. Think PCB or wire 15G Upload a clock, with a sense too, and fortunately we do not do such a thing.

Channel homogenization well worth mentioning, this is the decisive factor in the development of high-speed SerDes, so I decided to spend some words to talk about.

Generally, real-world channels are low-pass characteristics, full of small capacitors, the so-called insulator molecules absorb energy in an electric field at high frequencies, coupled with the wire of the skin effect, so we want to the high-frequency signal can not walk far to look like, such as a frequency characteristic of the following channels (green line).

As shown, the corresponding frequency 28Gbps on the signal energy is attenuated 30db, only 3% of the voltage amplitude; the frequency corresponding to 56Gbps even worse, 65db means the signal voltage swing in less than one thousand one minute. In this channel, the sender of a data eye pretty perfect:

The receiving end will become like a pile of garbage:

What are unidentifiable right. However, after our brilliant engineers who worked hard, uniform switch is turned on, the signal becomes this:

What magic? I feel very magical, electronic engineers I knew the first time I saw this, did not feel the magic.

Here is an important question, as with the three magic weapons, they can only use the serial port it?
The answer is obviously not, you can use the serial port, parallel port as we can. Parallel why not?

This differential signal Needless to say, parallel wires already more than enough, but also the number of double again? System engineers will kill.

CDR not be very meaningful, anyway, your parallel port speed is not high, the way a bunch of data lines pass under the clock, likened the receiving end do CDR resampled every save more data.

Channel uniform belonging to the Dragon technology, without the differential signal, then will pass hundreds of M, already lacks attenuation by doing this? Or consider the various types of noise crosstalk issues now.

So the answer is ready to come out. Why faster than the parallel port? Because the serial features and application scenarios, determine which is more suitable for some of the increase may be a single channel rate design methods that are used in parallel is not appropriate.

From existing applications opinion, it requires sustained high-bandwidth applications, often using high-speed serial interface, an insufficient bandwidth plus a variety of video network applications, basically the same. Some legacy applications speed is not high, there are some unexpected need high-bandwidth applications, parallel still alive, such as the very special DDR. Although XDR / GDDR / HMC / HCM These new standards are trying to introduce SerDes, but the special nature of the DRAM industry still continues to make parallel alive.


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